Codificatore 2D-DCT hardware
di Pietro Sarro, Cataldo Sasso, Giuseppe Scappatura
Copyright © 2006 P. Sarro, C. Sasso, G. Scappatura
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Vi presento qui il lavoro che abbiamo svolto per l'esame di Sistemi Integrati.
Si trattava di implementare in VHDL un codificatore 2-D DCT. Tutti i files relativi
al progetto sono reperibili nel file dct.zip. Di seguito riporto il testo delle specifiche
richieste per lo sviluppo del progetto.
The Discrete Cosine Transform
The discrete cosine transform (DCT) and the inverse discrete cosine transform
(IDCT) are substantial performance bottlenecks in the contemporary visual datacompression
algorithms (JPEG, MPEG, etc.). Implementing DCT/IDCT, as anASIC is a design
solution, which meets the real time processing requirements.
DCT and IDCT have been widely used in video data compression standards. The
decorrelation and energy compaction properties of the transform have been exploited
to achieve high compression ratios in MPEG and JPEG. The N-point 1-D DCT is
DCT and IDCT are highly computational intensive, which creates prerequisites
for performance bottlenecks in systems utilizing them. To overcome this problem,
a number of algorithms have been proposed for more efficient computations of
You are required to implement the 2-D DCT on a block of 8x8 samples using
the Van Eijdhoven and Sijstermans approach. This algorithm is a slight modification
of the original Loeffler algorithm, which provides one of the most computationally
efficient 1-D DCT calculations. The chioce of the algorith is not mandatory,
just an advice, any other motivated solution is appreciated.
Some detail about the algorithm can be retrived from the article "DCT and
IDCT Implementations on Different FPGA Technologies" by Khurram Bukhari,
Georgi Kuzmanov and Stamatis Vassiliadis of the Computer Engineering Lab, Delft
University of Technology and in the reference of the paper itself.
Your deliverable consists of:
- maximum 10 pages synthetic project document, including
data-sheet of your design with input/output signal description, protocol
and timing of I/O signals (if needed), and description of the testing environment;
short description of the internal architecture and your design choices
using text, schematics, simulation waveforms and state-transistion diagrams
or state-transition matrices;
post-synthesis results, that is complexity and performance
- a zipped file containing the following directories;
src contains the VHDL source files of your design, including the testbench.
Please write all your VHDL according to the style of the template posted on
the course website.
syn contains synthesis script and post-synthesis report;
doc contains the documentation in pdf format.